Title: Sub-System and interconnections specifications
Date: Sep. 2018
Abstract: This document presents the specifications for the elements to be designed in WP2 and WP3. The document starts from the system specification defined in deliverable D1.2 and reviews the system architecture. Then it describes the transceiver demonstrator that will be developed in the project. The arrangement in chips of the ICs to be designed using ST technology is also stated. The document follows a top-down approach to analyse the architecture and provide a first specification for all the blocks to be designed within the project and their interfaces.