Title: Sub-System and interconnections specifications
Date: 16 may 2019
Abstract: This document presents the updated specifications for the elements to be implemented in WP2 and WP3. It is based on D1.3, which has been reviewed after obtaining measurement results from WP2-WP3 and more realistic simulation results. The document follows the same structure as D1.3: It starts from the system specification defined in deliverable D1.2 and reviews the system architecture. Then, it describes the transceiver demonstrator that will be developed in the project. The arrangement in chips of the ICs to be designed using ST technology and the PCB partitioning is also stated. The document follows a top-down approach to analyze the architecture and provide a set of specifications for all the blocks to be designed within the project and their interfaces.