Deliverable D2.2.1

Title: D-Band frequency synthesis design
Date:  Sep. 2018
Dissemination: Confidential
Abstract: This document describes part of the activities of Task 2.2 in WP2. The report presents the design consideration and circuits aimed at the implementation of a D-band frequency synthesis chain. The chain is intended to be used in a low-cost SiGe BiCMOS transceiver demonstrating the feasibility of a link data rate up to 100 Gb/s in D-band.
The report starts from the specifications defined in tasks 1.2 and 1.3, reported in the corresponding deliverables, and describes how the proposed architecture can achieve them. After an overview of the overall architecture, design concepts and relevant simulation results, together with the details of the physical implementation in ST’s BiMOS055 technology are presented.
Frequency synthesis is done by using an X-band signal source and then multiplying the signal frequency up to D-band using a multiplication factor of 12. Design of a multiply-by-6 chip which up-converts the X-band signal up to E-band (70-to-80GHz) is presented in detail with simulation results, layout and full chip description. A key design challenge is keeping low spurious tones, and a new circuit topology is proposed, able to reach the target specifications at low power consumption. The design of a frequency doubler generating the D-band LO signal (140-to-160GHz), starting from a driving signal centred at 75GHz, is also presented. This doubler will be integrated together with the D-band up/down converters of the full transceiver.
The report concludes with a comparison of the most important performance parameters of the designed chips with those of the state-of-the-art works in technical literature and also commercially available products.
Keywords: Frequency Multiplier, Frequency Synthesis, Frequency Tripler, Frequency Doubler, Phase Locked Loop, Coupled Transformers, millimetre-wave, D-band communications, phase noise, BiCMOS, SiGe.