Deliverable D2.5

Title: First report on D-band frequency synthesis test
Date:  May 2019
Dissemination: Confidential
Abstract: This Deliverable reports measurement results of a first test chip, which will be part of the frequency synthesis chain in the D-band transceiver. The Deliverable starts by presenting the frequency synthesis architecture and a summary of the specifications outlined in WP1. A key component of the chain is a frequency multiplier by 6, generating an E-band (75GHz) output starting from an X-band (12.5GHz) signal. This document reports the measurement setup and results for this chip. This chip comprises the cascade of a frequency tripler and a frequency doubler. An intermediate buffer allows separate testing of the two blocks. Measurements on the frequency tripler confirm the expected results and fully meet specifications. The tripler, based on a novel circuit topology, operates over a 16% fractional bandwidth and achieves a remarkable improvement of spurious tones rejection against state of the art. Measurements on the frequency doubler revealed an output power lower than expected from simulations performed at tape-out. After careful investigation, subtle wiring parasitic effects, not properly accounted, are causing the power reduction. New simulations reproduce correctly the measurement results, giving good confidence on the issue. Activity is currently in progress to fix the layout in a second test chip version, which will be sent for fabrication in the next tape-out.
Keywords: Frequency Multiplier, Frequency Synthesis, Frequency Tripler, Frequency Doubler, Phase Locked Loop, Coupled Transformers, millimetre-wave, D-band communications, phase noise, BiCMOS, SiGe.